1. Field of the Invention
The present invention generally relates to a method for forming fine patterns of a semiconductor device and more specifically, to a method for forming fine patterns of a semiconductor device, wherein a first lower layer pattern having a width of two minimum line width and a space pattern is formed on a semiconductor substrate prior to a C-HALO implant process and the first lower layer pattern is etched to separate into a second lower layer pattern having a width of two minimum line widths and a space pattern.
2. Description of the Related Art
Generally, fabricating semiconductor devices such as Dynamic Random Access Memory (“DRAM”), Static Random Access Memory (“SRAM”), and LOGIC requires to employ a lithography process using a short wavelength light source for obtaining fine patterns.
The lithography process includes depositing a photoresist film over a semiconductor substrate, exposing the photoresist film using a laser light source the wavelength of which is 365 nm, 248 nm, 193 nm, or 153 nm through an exposure mask having circuit patterns and then developing the exposed photoresist film.
However, the above-described lithography process is required to be performed in an exposure apparatus using a short wavelength light source and a photoresist material highly sensitive to short wavelength light must be used. As a result, formation of fine patterns having a line width less than 0.1 μm is not facile.
Moreover, when a C-HALO implant process is performed to implant an impurity into a space between every other gate patterns having a less than 0.1 μm line width in a semiconductor device such as 90 nm DRAM to improve its electrical characteristics such as threshold voltage Vt, the implant process cannot be performed perfectly since the gate patterns have a narrow space therebetween and a large step difference.
FIGS. 1a through 1d are cross-sectional views illustrating a conventional method for forming fine patterns of semiconductor device.
Referring to FIG. 1a, a lower layer 3 to be etched is deposited on a semiconductor substrate 1. A first photoresist film (not shown) is deposited on the lower layer 3, and then subjected to an exposure and development process using an exposure mask (not shown) having fine patterns to form a first photoresist film pattern.
Referring to FIG. 1b, the lower layer 3 is etched via an etching process using the first photoresist pattern 5 as an etching mask to form a first lower layer pattern 3-1.
The width of the first lower layer pattern denoted as ‘a’ ranges from 10 nm to 150 nm, and a width of a space between the patterns ranges from 10 nm to 150 nm.
Referring to FIG. 1c, a second photoresist film 7 is formed on the semiconductor substrate 1 including the first lower layer pattern 3-1.
Referring to FIG. 1d, a second photoresist pattern 7-1 for a subsequent C-HALO implant process is formed via an exposure and development process. The second photoresist pattern 7-1 exposes spaces between every other lower layer pattern 3-1.
The semiconductor substrate 1 is then subjected to a C-HALO implant process 9 using Br ions to form an ion-implanted region 13.
When microscopic patterns below 0.1 μm, for example 0.05 μm using the short wavelength light source having a wavelength of 248 nm or 193 nm, the second photoresist layer pattern 7 is not completely removed during the development process, thereby causing a step difference due to the remaining photoresist pattern 11 at the bottom of the space as shown in FIG. 1e. 
This phenomenon cannot be prevented in a subsequent development process such as a wet etching process even when a high-resolution photoresist material is used because the space between the patterns is narrow and deep.
Particularly, as an exposure apparatus having a high numerical aperture (“NA”) is widely used, depth-of-focus (“DOF”) is decreased and completely removing the photoresist material between the lower layer patterns having a large step difference is almost impossible.
Accordingly, when the photoresist film remains between the patterns, a shadow phenomenon renders the subsequent C-HALO implant process unstable. A collapse of the fine patterns on the lower layer pattern occurs, generating process defects, and decreasing the yield rate of the semiconductor device.